The demand for semiconductor integrated circuit (IC) devices such as computer chips with high circuit speed and high circuit density requires the downward scaling of feature sizes in ultra-large scale integration (ULSI) and very-large scale integration (VLSI) structures. The trend to smaller device sizes and increased circuit density requires decreasing the dimensions of interconnect features and increasing their density. An interconnect feature is a feature such as a trench or via formed in a dielectric substrate which is then filled with metal to yield an electrically conductive interconnect. Copper, having better conductivity than any metal except silver, is the metal of choice since copper metallization allows for smaller features and uses less energy to pass electricity.
A conventional semiconductor manufacturing process is the damascene system. The damascene process begins by etching the circuit architecture into the substrate's dielectric material. The architecture is comprised of a circuitry pattern comprising a combination of the aforementioned trenches and vias. In the context of semiconductor integrated circuit device manufacture, substrates include semiconductor wafers and chips, typically silicon wafers and silicon chips, although other semiconductor materials, such as gallium arsenide are used as well. A dielectric film, such as, for example, SiO2 or low-κ dielectrics, is typically deposited by conventional methods on the surface of the semiconductor wafer or chip and then etched, by conventional lithography, to achieve the circuitry pattern.
Next, a barrier layer is laid over the dielectric film having the patterned circuit architecture therein to prevent diffusion of the subsequently applied copper layer into the substrate's junctions. The barrier layer is deposited since copper has a tendency to diffuse into the semiconductor's junctions, thereby disturbing their electrical characteristics. The barrier layer typically includes a refractory metal nitride and/or silicide, such as titanium or tantalum. Of this group, tantalum nitride is one of the most desirable materials for use as a barrier layer. Tantalum nitride has one of the lowest electrical resistivities of the metal nitrides and is also a good barrier to prevent copper diffusion, even when relatively thin layers are formed (e.g., about 20 angstroms or less). A tantalum nitride layer is typically deposited by conventional deposition techniques, such as physical vapor deposition (PVD), atomic layer deposition (ALD) or chemical vapor deposition (CVD).
Tantalum nitride has negative characteristics, which include poor adhesion to the copper layer deposited thereon. Poor adhesion of the subsequently deposited copper layers can lead to poor electromigration in the formed device and possibly cause process contamination issues in subsequent processing steps, such as during a chemical mechanical polishing (CMP) process. A tantalum nitride layer exposed to oxygen sources or other contaminants may cause the exposed surface of the tantalum nitride layer to oxidize thus preventing the formation of a strong bond to the subsequently deposited copper layer. The interface between a tantalum nitride barrier layer and a copper layer is likely to separate during a standard tape test.
Deposition of the barrier layer may be followed by physical or chemical vapor deposition of a copper seed layer to provide electrical conductivity for a sequential electrochemical process. Conventional PVD copper seeding may not be extendible to 22 nm technology node or beyond. Chemical seeding alternatives and direct plating on barriers such as Ta/TaN, Ti/Ti/N, W/WN or ruthenium materials have been investigated in recent years to achieve conformal step coverage. However, adhesion of copper deposits through direct electrochemical plating processes on those resistive barriers other than ruthenium is an issue. Even though ruthenium may not be an effective barrier, it is a promising alternative seed layer because it has excellent adhesion to both copper and the underlying barrier layer, and it also provides the feasibility of direct electrolytic deposition or electroless deposition.
Although ruthenium is a fairly conductive material, its sheet resistance at nano-scale thickness is still too high to be electrolytically plated uniformly. Global uniformity of electrolytic copper deposition (ECP) on ruthenium is currently unacceptable due to significant degree of terminal effect. PVD copper flash and other processes have been explored for possible reduction of terminal effect. Electroless copper deposition is an attractive alternative to warrant uniform seed coverage locally and globally for sequential electrochemical copper gapfill, and possibly to achieve direct void-free gapfill on ruthenium substrates.
After deposition of barrier layer and seeding, vias and trenches that define the circuit architecture are filled with copper by plating (such as electroless and electrolytic), sputtering, plasma vapor deposition (PVD), and chemical vapor deposition (CVD). It is generally recognized that electrolytic deposition is the best method to apply copper since it is more economical than other deposition methods and can flawlessly fill into the interconnect features (often called “bottom up” growth). After the copper layer has been deposited, excess copper is removed from the facial plane of the dielectric by chemical mechanical polishing, leaving copper in only the etched interconnect features of the dielectric. Subsequent layers are produced similarly before assembly into the final semiconductor package.